The present invention relates to a method for making semiconductor devices, in particular, those that include decoupling capacitors.
Decoupling capacitors may be included in an integrated circuit to reduce inductive noise. To decrease inductance., and cost, decoupling capacitors may be formed on the chip instead of elsewhere within the device""s package. Examples of methods for forming semiconductor devices that include on-die decoupling capacitors are described in Ser. No. 09/965,972, xe2x80x9cFabrication of 3-D Capacitor with Dual Damascene Process,xe2x80x9d filed Sep. 27, 2001; Ser. No. 09/895,362, xe2x80x9cOn-Die De-Coupling Capacitor Using Bumps or Bars and Method of Making Same,xe2x80x9d filed Jun. 29, 2001; and Ser. No. 09/962,786, xe2x80x9cTop Electrode Barrier for On-Chip Die De-Coupling Capacitor and Method of Making Same,xe2x80x9d filed Sep. 24, 2001xe2x80x94each assigned to this application""s assignee.
FIG. 1 represents a device that Ser. No. 09/965,972 describes in which on-die decoupling capacitor 50 separates conductor 40 from conductor 17. Capacitor 50 includes first conductive barrier layer 19, high k dielectric layer 20, and second conductive barrier layer 21. Because the barrier layers and the dielectric layer line the via and trench, the capacitor covers more area than a planar capacitor would cover. As a result, this 3-D capacitor may provide a 4xc3x97 increase in capacitance, when compared to the capacitance that a planar capacitor would be expected to generate.
FIG. 2 represents a device, which Ser. No. 09/895,362 describes, in which a bump connection contacts an on-die decoupling capacitor. The decoupling capacitor, which comprises upper electrode 14, high k dielectric layer 16 and lower electrode 18, separates Vcc line 72xe2x80x94formed in the device""s upper metal layerxe2x80x94from bump metal 84. FIG. 3 represents a device, which Ser. No. 09/962,786 describes, in which barrier layer 12 is formed on upper electrode 14 of the decoupling capacitor stack, which also includes high k dielectric layer 16 and lower electrode 18.
When making on-die decoupling capacitors, the lower electrode may be made from tantalum nitride and the high k dielectric layer may be made from tantalum pentoxide. When such a high k dielectric material is deposited on such a substrate, e.g., by using a conventional atomic layer chemical vapor deposition process, the nucleation density of the resulting high k dielectric layer may be unacceptable. As a result, the dielectric layer may contain a significant number of pinholes.
Forming the lower electrode from titanium nitride instead of tantalum nitride may mitigate nucleation problems. Because, however, titanium nitride may be more difficult to etch than tantalum nitride, it may not be desirable to substitute titanium nitride for tantalum nitride to form the lower electrode. As an alternative to making that substitution, forming a very thin aluminum oxide seed layer on a tantalum nitride layer prior to depositing a tantalum pentoxide layer on the tantalum nitride layer may improve the nucleation density for the tantalum pentoxide layer. Because adding such a seed layer to the high k dielectric layer will increase the effective thickness of the high k film, the presence of the seed layer may reduce the capacitance density in an unacceptable manner.
Accordingly, there is a need for an improved process for making an on-die decoupling capacitor. There is a need for such a process that enables a dielectric layer with an acceptable nucleation density to be formed on a barrier layer. There is also a need for such a process for making an on-die decoupling capacitor that forms on a lower electrode, e.g., one including tantalum nitride, a high k dielectric layer, e.g., one including tantalum pentoxide, that does not have a high pinhole density. The method of the present invention provides such a process.